1. Field of the Invention
The present invention relates to a test apparatus for a memory with a redundancy circuit and, more particularly, to a test apparatus for rapidly determining whether a defective chip can be remedied using a redundancy circuit.
2. Description of the Related Art
In recent years, a redundancy circuit technique has become essential as capacities of semiconductor memories increase. A redundancy circuit adds memory cells of an auxiliary row or colunn to a normal memory array. When a defective row or column or a defective bit is present in the normal memory array, the redundancy circuit replaces it with the above auxiliary row or column, thereby remedying a defective chip.
Conventionally, whether a defective chip can be remedies is determined using the redundancy circuit as follows. That is, an operation test of a completed semiconductor memory is performed using a semiconductor memory tester. In this case, a determination result of operability of the memory under test is fetched in a unit called an address fail memory in the semiconductor memory tester. The address fail memory has the same capacity as a larger capacity than that of the memory under test. Thereafter, whether the defective chip can be remedied is determined in accordance with a suitable algorithm corresponding to the number of auxiliary rows or columns of the memory under test. In a normal defect remedy algorithm, the auxiliary rows or columns are sequentially assigned to rows or columns from one having a largest number of defective bits, thereby performing remedy determination by determining whether the number of the rows or columns is sufficient.
In a semiconductor memory, the first test is performed after manufacturing steps for respective semiconductor elements which constitute the memory are finished. When a defective memory cell is present, a program of a redundancy control circuit is executed to remedy the cell. After the program is executed, the semiconductor memory is tested again and various assembly steps are peformed for good memories only. In the first test, a complicated test is performed under strict conditions in order to reduce the frequency of occurrence of defects in the subsequent steps.
However, in a determination method according to the conventional technique, whether the defective chip can be remedied is determined after the operation test for the memory under test is finished. For this reason, in order to determine whether the defective chip can be remedied using the redundancy circuit, a time obtained by adding a time for the operation test of the memory under test to a time for determining remediableness on the basis of the operation test result, Since this test is performed after the manufacturing steps of the respective semiconductor elements are finished, it is performed regardless of whether a memory is good or defective. In addition, if a memory is defective, the test is performed regardless of whether the memory can be remedied by the redundancy circuit. Therefore, the test time is undesirably prolonged. In general, determination of remediableness of a memory under test using the redundancy circuit must be performed for a large number of chips in the form of a wafer. Therefore, even when a chip is determined to be unremediable because the number of defective bits is too large and, therefore, is excluded, it is inefficient to carry out the above determination for all remaining chips. Especially, carrying out of the above test to a large number of chips in a manufacturing line is inefficient and increases manufacturing cost. In addition, since recent semiconductor memories have a large capacity, are operated at a high speed, and are highly functional, a tester for these memories must have high quality and therefore is expensive. Since such a tester is used for a long period of time, cost for the test is undesirably increased.